Parallel computing developed between the 1960 and the 1990s, it entailed of the designed processors that were very expensive. Due to increase in the performance of the commodity, the CPUs developed to the HPC machines towards the multi-based computers. The HPC occur currently connected to the commodity PCs. Based on the interconnection of diverse networks, there is a shared mode in delivering a certain message within a given span of time, and this means that all the processors have the ability of viewing each message redirected to them. The switched medium aims at supporting the point-to-point messages entailed between the pair of processors. This medium gives room for the concurrent messages.
The network topologies have specific measurements, the diameter occurs as the largest distance between the switch nodes, while the bisection width comprises of the minimal number of edges situated between the switch nodes, removed with the aim of splitting the network in two. The edges per each switch node occur as the best under conditions that the edge length has a constant maximum edge length. The network topologies comprise of the following networks;
- 2-D Mesh network
- Butterfly Network
- Hypercube Network
- Hypertree Network
- Binary Tree Network
According to the processor arrays, the vector computers comprise of instructions comprising of vectors and scalars. The pipelined vector processor passes the vectors to the CPU, where the pipelined arithmetic units perform aided by Cray-1 and Cyber-205. The processor arrays develops as the sequential computer that is connected to a group of identical, synchronized processing aspects that apply similar operation on different sets of data.
The processor array develops in a distinct manner whereby, the front side entails of the regular uniprocessor, the backend comprises of arrays of simplified processors with their own local memory. The front end has the function of reading instructions and data while broadcasting them to the backend array. Examples of the processor array instructions passed to the backend array include the SSE, the MMX instructions, and the GPUs. However, it is evident that not all the instructions map well to the processor arrays.
The Multiprocessors are centralized and they occur as straightforward extensions of the uniprocessor. Each of the uniprocessor shares similar buses containing collinear memory and the IO. The cache coherence issue is handled through a process referred as ‘snooping’. All the CPU caches function effectively before writing. All the cache copies invalidate resulting to a re-read. The distributed multiprocessors exist in diverse machine usually associated through an interconnection of networks known as the non-uniform memory access (NUMA) multiprocessors since the access of memory varies depending on many conditions. Snooping does not function effectively during cache coherence, this is because the directory-based protocols are utilized in places where the sharing of information in the storage of each memory block.
The multi-computers have a high performance built for the hardware commodity, usually stored in racks, where all the machines function through a certain network. These computers are either asymmetrical or symmetrical. The Flynn Taxonomy aids in the organization of SISD (Single Instruction Single Data), SIMD (Single Instruction Multiple Data), MISD (Multiple Instruction Single Data) and the MIMD (Multiple Instruction Multiple Data). These features aid in systolic arrays, which entails of signal processing, and they are involved in multicomputer and multiprocessors.
